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Preview of Intel Itanium 9500 Specifications

The Internet community is actively discussing new Intel's development, processors Poulson, that belongs to the tenth generation of Intel Itanium. All previous data about the upcoming product were vague and void of official proofs. Currently, the data are more ample and allow the community to study the future processor in more details. Thus, Intel Itanium 9500, codenamed Poulson, will be presented by four models the release of which is planned for early autumn.

The crystal of Poulson processor will consist of 3.1 billion transistors that are called to form eight computing cores. Each core counts up 89 million transistors and the pipeline width is doubled to twelve instructions. This way CPU developers implement more efficient approach towards transistor budget. Just for comparison purposes, Poulson's predecessor, Tukwila, counted 109 billion transistors per core.

To continue, Poulson CPUs will accommodate a couple of cache memory arrays, five channels of QPI bus, system logic components, and two memory controllers Scalable Memory Interconnect which will support 512 GB of DDR3 memory per slot. In general, Poulson CPU will be equipped with 54 Mb of cache memory; 2Mb of L2 memory, 2.2 Mb of memory catalog, 4 Mb of L2 memory instructions, 3.6 Mb of last level tags, 169 Kb of second level instruction tags, and 32 Mb of L3 memory which are divided between the eight cores in 4 Mb blocks. Each of the cores includes 16 Kb of instruction cache and 16 Kb of data cache. All integrated memory supports error correction standards.

The central part of the crystal is furnished with 10-channel router which exert control over memory and input/output systems. It also links four QPI channels in the top segment with a couple of one-half channels in the bottom segment.
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  • 23 July 2012, 13:53
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